Conventional Set-associative Cache Research Articles

Segmented Tag Cache: A Novel Cache Organization for Reducing Dynamic Read Energy

A set-associative cache organization is widely used to achieve a high hit-rate in modern caches, leading to a considerable enhancement in the system performance. In a conventional set-associative cache, tag and data arrays are simultaneously accessed to achieve fast access, but doing so causes a large amount of energy consumption. Previous attempts, such as way prediction and sequential tag access for energy reduction, are still associated with substantial energy consumption due to the tag access. This paper presents a new cache organization termed Segmented Tag Cache (STC), which reduces the amount of energy consumed during the tag access. The proposed organization initially implements a new tag organization that supports partial tag access. More specifically, the tag array is segmented into two parts, and partial tag access only reads low-order part of the tag. A cache access scheme suitable for the proposed tag organization then are developed. Under the scheme, the delay of the tag organization is hidden by the data access delay, avoiding an increase in the overall cache access time to be maintained. Simulation results show that the STC reduces the energy-delay product by approximately 58 percent compared to the conventional cache organizations with a negligible performance penalty.

A Varying Processor Cache Sets Architecture

Any processor cache has three parameters capacity, line size and associativity. Usually all three are fixed at design time. Algorithms to have variable cache sets are proposed in literature. This paper proposes a method to have variable cache sets logically. The cache comes with fixed sets. The cache is visualized to have logically any number of sets greater than or equal to one. An algorithm for line placement/replacement is proposed in this paper for this model. The proposed model is simulated with SPEC2K benchmarks using Simplescalar Toolkit for two level inclusive set associative cache system. A power saving of 8.4% for L1 cache size 512x4, 17.58% for 1024x4 and 31.3% for 2048x4 is observed compared with traditional set associative cache of same size. A power saving of 7.53% compared with model proposed in literature for L1 size 512x4, 7.64% for 1024x4 and 7.645% for 2048x4 is observed. The L2 cache size is fixed at 2048x8. The average memory access time (AMAT) is found to degrade compared with conventional set associative cache by 19.63% for L1 size of 512x4, 24.68% for 1024x4 and 2048x4. (Abstract)

Newcache: Secure Cache Architecture Thwarting Cache Side-Channel Attacks

Newcache is a secure cache that can thwart cache side-channel attacks to prevent the leakage of secret information. All caches today are susceptible to cache side-channel attacks, despite software isolation of memory pages in virtual address spaces or virtual machines. These cache attacks can leak secret encryption keys or private identity keys, nullifying any protection provided by strong cryptography. Newcache uses a novel dynamic, randomized memory-to-cache mapping to thwart contention-based side-channel attacks, rather than the static mapping used by conventional set-associative caches. In this article, the authors present an improved design of Newcache, in terms of security, circuit design and simplicity. They show Newcache's security against a suite of cache side-channel attacks. They evaluate Newcache's system performance for cloud computing, smartphone, and SPEC benchmarks and find that Newcache performs as well as conventional set-associative caches, and sometimes better. They also designed a VLSI test chip with a 32-Kbyte Newcache and a 32-Kbyte, eight-way, set-associative cache and verified that the access latency, power, and area of the two caches are comparable. These results show that Newcache can be used as L1 data and instruction caches to improve security without impacting performance.

V-SET CACHE: AN EFFICIENT ADAPTIVE SHARED CACHE FOR MULTI-CORE PROCESSORS

Development in VLSI design allows multi- to many-cores to be integrated on a single microprocessor chip. This increase in the core count per chip makes it more critical to design an efficient memory sub-system especially the shared last level cache (LLC). The efficient utilization of the LLC is a dominant factor to achieve the best microprocessor throughput. Conventional set-associative cache cannot cope with the new access pattern of the cache blocks in the multi-core processors. In this paper, the authors propose a new design for LLC in multi-core processor. The proposed v-set cache design allows an adaptive and dynamic utilization of the cache blocks. Unlike lately proposed design such as v-way caches, v-set cache design limits the serial access of cache blocks. In our paper, we thoroughly study the proposed design including area and power consumption as well as the performance and throughput. On eight-core microprocessor, the proposed v-set cache design can achieve a maximum speedup of 25% and 12% and an average speedup of 16% and 6% compared to conventional n-way and v-way cache designs, respectively. The area overhead of v-set does not exceed 7% compared to n-way cache.

Different access mechanisms for set-associative cache architecture for reduced power consumption

In recent years, power consumption has become one of the most critical design concern. Due to lower miss rate, set-associative caches are usually employed to improve embedded system's performance. However, a conventional set-associative cache implementation is not power efficient. Thus, in order to achieve low-power consumption, novel set-associative cache architectures have been proposed in which efficient accessing of tag bits and the data bits takes place in two phases unlike the conventional set-associative cache architectures. The behavioural modelling of the cache architectures was done using Verilog Hardware Description Language (HDL). The synthesis results illustrate that the proposed parallel and sequential set-associative cache architectures showed significant power reduction of 34.92% and 35.36% on an average as compared to conventional parallel and conventional sequential set-associative cache architectures, respectively.

An Energy Efficient Set Associative Cache Algorithm

associative caches have fixed ways. Entire cache is enabled during cache operation. This paper proposes cache architecture mapping cache line to fixed cache way of mapped set. The address is mapped to set as in conventional set associative cache. The tag value of the mapped line is divided into blocks of size of number of cache ways. The average of maximum and minimum frequency of this division is the mapped way. The proposed model is simulated with SPEC2K benchmarks. The average memory access time degradation of 3.8% is seen over traditional set associative cache. The energy saving of 49% is observed in proposed model.

A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems

Modern embedded processors commonly use a set-associative scheme to reduce cache misses. However, a conventional set-associative cache has its drawbacks in terms of power consumption because it has to probe all ways to reduce the access time, although only the matched way is used. The energy spent in accessing the other ways is wasted, and the percentage of such energy will increase as cache associativity increases. Previous research, such as phased caches, way prediction caches and partial tag comparison, have been proposed to reduce the power consumption of set-associative caches by optimizing the cache access mode. However, these methods are not adaptable according to the program behavior because of using a single access mode throughout the program execution. In this paper, we propose a behavior-based adaptive access-mode for set-associative caches in embedded systems, which can dynamically adjust the access modes during the program execution. First, a program is divided into several phases based on the principle of program behavior repetition. Then, an off-system pre-analysis is used to exploit the optimal access mode for each phase so that each phase employs the different optimal access mode to meet the application's demand during the program execution. Our proposed approach requires little hardware overhead and commits most workload to the software, so it is very effective for embedded processors. Simulation by using Spec 2000 shows that our proposed approach can reduce roughly 76.95% and 64.67% of power for an instruction cache and a data cache, respectively. At the same time, the performance degradation is less than 1%.

Low-power L2 cache design for multi-core processors

A low-power set-associative L2 cache design for a multi-core processor is proposed. Since this way-predicting L2 cache (WP-L2) predicts a destination way and accesses only the predicted way, it consumes less energy than a conventional set-associative L2 cache. Exploiting access patterns of an L2 cache, WP-L2 is based on two prediction logics; a look-ahead buffer (LAB) predicts the next sequential cache block and a way-affinity table (WAT) records the way number of the previous L2 cache access. Combining the logics, WP-L2 predicts correct ways for about 83% of L2 cache accesses and reduces about 22% of access latency and 44% of energy consumption compared to the conventional eight-way set-associative L2 cache.

A deterministic way-prediction scheme using power-aware replacement policy

This research is to design a low power set-associative cache for embedded processors without additional delay or performance degradation. For this goal, deterministic way selection logic with power-aware replacement policy is designed to enable only one way of set-associative cache as in the direct-mapped cache. Delay analysis shows that the cache access time is almost the same as that of conventional set associative cache with additional way selection logic. Proposed architecture exploits the trade-offs between power and performance to achieve power reduction with the least performance loss. As the result of those approaches, simulation shows that the proposed architecture can reduce unit accessing power consumption by 59% over conventional set-associative caches with average 0.06% of negligible performance loss.

WCRT analysis for a uniprocessor with a unified prioritized cache

In this paper, we investigate the problem of inter-task cache interference in preemptive multi-tasking real-time systems. A prioritized cache is used to reduce cache conflicts among tasks by partitioning the cache. Cache partitions are assigned to tasks according to their priorities. We extend a known tool, SYMTA, in order to estimate the Worst Case Execution Time of tasks executing on a uniprocessor with a unified prioritized L1 cache. Furthermore, we apply a formal timing analysis approach to estimate the Worst Case Response Time of tasks using the prioritized cache. The prioritized cache is compared to a conventional set associative cache of the same size. Our experiments show that the WCRT estimate can be reduced up to 50% when a prioritized cache is used.